1. Field of the Invention
The present invention generally relates to a nano tube cell and a memory device using the same, and more specifically, to a technology of reducing the whole memory size by embodying a cross point cell using a capacitor and a PNPN nano tube switch which does not require an additional gate control signal.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional DRAM cell.
A conventional DRAM cell comprises a transistor TR and a capacitor CAP which is connected between a plate line PL and one terminal of the transistor TR. The transistor TR performs a switching operation depending on a state of a word line WL to connect the capacitor CAP to a bit line BL.
Here, a switching device of the conventional DRAM cell is a NMOS transistor whose switching operation is controlled by a gate control signal. However, when a cell array is embodied by using the above-described NMOS transistor as a switching device, the whole chip size is increased.
Meanwhile, a refresh characteristic of the DRAM cell is determined by the leakage current characteristic of the NMOS transistor. When the channel length of the NMOS transistor is decreased to a nano meter (1/one billion) scale, short channel leakage current increases more by the current characteristic of a sub threshold voltage Sub Vt of the NMOS transistor. As a result, it is difficult to satisfy the refresh characteristic of the DRAM cell. Also, junction leakage current is generated in a storage node terminal which occupies a relatively large area in the DRAM cell.
Therefore, it is necessary to reduce the whole memory size by embodying a cross point cell using a capacitor and a PNPN nano tube switch which does not require an additional gate control signal.